general description the MAX3784 5gbps equalizer provides compensation for transmission-medium losses in up to 40in of fr4. it is optimized for short run length, balanced codes such as 8b10b, as found in multiplexed 1.25gbps ethernet systems. the equalizer uses differential cml data inputs and outputs. a standby mode provides low power when the part is not in use. the MAX3784 is available in a 4mm 4mm 16-pin qfn package that consumes only 185mw at +3.3v. features spans 40in (1m) of fr4 pc board 0.18ui deterministic jitter up to 40in low power consumption: 185mw equalization reduces intersymbol interference single +3.3v supply standby mode small 4mm 4mm 16-pin qfn package MAX3784 5gbps pc board equalizer ________________________________________________________________ maxim integrated products 1 1 2 3 4 5678 9 10 11 16 12 13 14 15 v cc v cc v cc in+ in- gnd gnd gnd n.c. n.c. n.c. n.c. n.c. en out+ out- note: the exposed pad must be soldered to supply ground for correct thermal and electrical performance. MAX3784 top view qfn pin configuration line card +3.3v 5gbps +3.3v t/r 1 rx tx t/r 2 rx tx t/r 3 rx tx t/r 4 rx tx t/r 1 t/r 2 t/r 3 t/r 4 rx tx 1.25gbps 1.25gbps 1.25gbps 1.25gbps switch rx tx switch card MAX3784 out in MAX3784 in out pc board backplane equalizer equalizer typical application circuit 19-2565; rev 0; 8/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX3784uge 0 c to +85 c 16 qfn ordering information applications chassis life extension
MAX3784 5gbps pc board equalizer 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +3v to +3.6v, t a = 0 c to +85 c. typical values are at v cc = +3.3v and t a = +25 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage, v cc .................................................-0.5v to +6v input voltage............................................(-0.5v) to (v cc + 0.5v) continuous output current ...............................-25ma to +25ma continuous power dissipation (t a = +85 c) 16-pin qfn (derate 25mw/ c above +85 c) ............1600mw operating ambient temperature range ................0 c to +85 c storage temperature range .............................-55 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units en = low 30 supply power en = high 185 250 mw 10hz < f < 100hz 100 100hz < f < 1mhz 40 supply noise tolerance (note 1) 1mhz < f < 2.5ghz 10 mv p-p latency from input to output 200 ps cml receiver input input voltage swing v in measured differentially at point a in figure 1 (note 2) 400 1000 mv p-p return loss 100mhz to 2.5ghz 15 db input resistance differential 80 100 120 ? equalization 20in 0.13 0.21 residual deterministic jitter, 5gbps table 1 (notes 2, 3, 4, 5) 40in 0.18 0.23 ui p-p 20in 0.08 0.14 residual deterministic jitter, 2.5gbps table 1 (notes 2, 3, 4, 5) 40in 0.13 0.28 ui p-p 20in 0.04 0.07 residual deterministic jitter, 1.25gbps table 1 (notes 2, 3, 4, 5) 40in 0.07 0.15 ui p-p random jitter (notes 5, 6) 1.3 1.9 ps rms cml transmitter output (into 100 ? 1 ? ) output voltage swing v o differential swing, measured differentially at point c in figure 1 400 600 mv p-p transition time t f, t r 20% to 80% (notes 5, 8) 30 45 60 ps output resistance single ended 40 50 60 ?
MAX3784 5gbps pc board equalizer _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +3v to +3.6v, t a = 0 c to +85 c. typical values are at v cc = +3.3v and t a = +25 c, unless otherwise noted.) note 1: allowed supply noise during jitter tests. note 2: test pattern. this is a combination of k28.5 characters running at the full bit rate and at one-quarter the bit rate. this simu - lates the multiplexing of four each 1.25gbps ethernet data streams. pattern (hex) 100 bits 00 ffff f0f0 ff 0000 0f0f (quarter rate k28.5+, quarter rate k28.5-) 3eb05 (k28.5 00 1111 1010 11 0000 0101) note 3: difference in deterministic jitter between reference points a and c in figure 1. note 4: signal source amplitude range is 400mv p-p to 1000mv p-p , differential. signal is applied differentially at point a as shown in figure 1. the deterministic jitter at point b must be from media-induced loss and not from clock-source modulation. deterministic jitter is measured at the 50% vertical level of the signal at point c. note 5: guaranteed by design and characterization. note 6: test pattern is k28.5 with 40in trace. note 7: on-chip pullup resistor of 40k ? typical. negative current indicates equalizer sources current. note 8: using 00 0001 1111 or equivalent pattern. measured over entire input voltage range, max and min media loss and within 2in of output pins. parameter symbol conditions min typ max units enable control pin input high voltage 1.5 v input low voltage 0.5 v input high current (note 5) -150 +10 ? input low current (note 5) -150 +10 ? signal source a backplane pc board MAX3784 equalizer in out l 40in 6mil line bc sma connector sma connector figure 1. test conditions parameter conditions min typ max units transmission line edge-coupled stripline 6 mil relative permittivity fr4 or similar 4.4 4.5 loss tangent fr4 or similar 0.02 0.022 metal thickness 0.7mil (0.5oz copper) 0.7 mil impedance differential 90 100 110 ? table 1. pc board assumptions (pc board material is fr4)
MAX3784 5gbps pc board equalizer 4 _______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, measurements done at 5gbps, 800mv p-p board input with 100-bit pattern from note 2 of the ec table ,t a = +25 c, unless otherwise noted.) 55mv/ div equalizer input eye diagram before equalization at 5gbps (40in, fr4, 6mil stripline) MAX3784 toc01 32ps/div 55mv/ div equalizer output eye diagram after equalization at 5gbps (40in, fr4, 6mil stripline) MAX3784 toc02 32ps/div 55mv/ div equalizer output eye diagram after equalization at 5gbps (20in, fr4, 6mil stripline) MAX3784 toc03 32ps/div 0 10 5 20 15 25 30 05 differential return loss MAX3784 toc04 frequency (ghz) return loss (db) 2 134 0 30 20 10 40 50 60 70 80 90 100 020 10 30 40 50 60 deterministic jitter vs. line length MAX3784 toc05 line length (in) (fr4 6mil stripline) deterministic jitter (ps) 1.25ghz 2.5ghz 5ghz 0 30 20 10 40 50 60 70 80 90 100 200 600 400 800 1000 1200 deterministic jitter vs. amplitude (20in fr4 stripline) MAX3784 toc06 input amplitude (mv p-p ) (figure 1, point a) deterministic jitter (ps) 1.25ghz 2.5ghz 5ghz 0 30 20 10 40 50 60 70 80 90 100 200 600 400 800 1000 1200 deterministic jitter vs. amplitude (40in fr4 stripline) MAX3784 toc07 input amplitude (mv p-p ) (figure 1, point a) deterministic jitter (ps) 1.25ghz 2.5ghz 5ghz 0 100 300 200 400 500 latency vs. temperature MAX3784 toc08 temperature ( c) latency (ps) 050 25 75 100 0 10 20 30 40 50 60 70 80 0 255075100 supply current vs. temperature MAX3784 toc09 temperature ( c) supply current (ma) i cc i shutdown
detailed description general theory of operation the MAX3784 adaptive equalizer extends the reach of transmission lines in high-frequency backplane inter- connect applications. it can be used for up to 20-bit cid (coded), nrz data operating at 5gbps as found in 4 1g ethernet (5gbps). internally, the MAX3784 is comprised of an equalizer control loop and limiting out- put driver. the equalizer reduces intersymbol interfer- ence (isi), compensating for frequency-dependent media-induced loss. the equalization control detects the spectral contents of the input signal and provides a control voltage to the equalizer core, adapting it to dif- ferent media. the equalizer operation is optimized for short-run, dc-balanced transmission codes. standby mode standby saves power when the equalizer is not in use. the en logic input must be set high or open for normal operation. logic low at en forces the equalizer into the standby state. cml input and output buffers the input and output buffers are implemented using cur- rent-mode logic (cml). equivalent circuits are shown in figures 3 and 4. for details on interfacing with cml, see maxim application note hfan-1.0: interfacing between cml, pecl, and lvds . the common-mode voltage of the input and output is above 2.5v. ac-coupling capaci- tors are required when interfacing this part with devices terminated in voltages such as 1.8v. values of 0.10? or greater are recommended. MAX3784 5gbps pc board equalizer _______________________________________________________________________________________ 5 pin description pin name function 1, 7, 12 v cc +3.3v supply voltage 2 in+ positive input, cml 3 in- negative input, cml 4, 6, 9 gnd supply ground 5, 8, 14, 15, 16 n.c. no connection. leave unconnected. 10 out- negative output, cml 11 out+ positive output, cml 13 en enable equalizer. a logic high or open selects normal operation. a logic low selects low-power standby mode. ep exposed pad connect to ground. the exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance. in+ in- en limiter 5gbps equalizer out+ out- v cc equalizer offset cancellation lowpass filter 50 ? 100 ? 40k ? 50 ? v cc MAX3784 figure 2. functional diagram
MAX3784 applications information alternate data rates the MAX3784 is optimized for automatic operation at 5gbps. equalization at other data rates, such as 1.25gbps and 2.5gbps, is possible. see the typical operating characteristics for deterministic jitter vs. line length and deterministic jitter vs. amplitude for typical performance at these data rates. layout considerations circuit board layout and design can significantly affect the MAX3784? performance. use good high-frequency design techniques, including minimizing ground induc- tance and connections and using controlled-imped- ance transmission lines for the high-frequency data signals. route signals differentially to reduce emi sus- ceptibility and crosstalk. solder the exposed pad to supply ground for proper thermal and electrical opera- tion. place power-supply decoupling capacitors as close as possible to the v cc pins. 5gbps pc board equalizer 6 _______________________________________________________________________________________ 50 ? 50 ? v cc 250 a figure 3. cml input equivalent circuit v cc 50 ? 50 ? out+ out- figure 4. cml output equivalent circuit
MAX3784 5gbps pc board equalizer _______________________________________________________________________________________ 7 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
MAX3784 5gbps pc board equalizer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
|
